As computers and processors become more powerful, more and more signal processing is being done in the digital domain. Digital signal processing can perform complex operations to manipulate input data to approximate real world analog signals, and the operations can be performed in real time, or the digital data can be stored for future processing. Since real world signals exist as analog signals, these analog signals need to be converted to equivalent digital signals.
Analog to digital converters (ADCs) are used in many applications, such as, for example, converting analog control signals in industrial applications, audio signals in music, photographic images in digital cameras, and video images in digital video cameras. As with most circuits, there are many different types of ADCs where tradeoffs are made for different limitations. Some, such as the “flash” ADC, are relatively expensive in circuitry and layout space and, accordingly, limited in resolution since every additional bit requires doubling of the number of comparators, but very fast in conversion speed. Others, such as the ramp ADC, can be fairly simple but slow in conversion time. And as the amount of resolution increases, the conversion time will increase.
Accordingly, a particular application needs to take into account various limitations and determine which design best serves its purposes. However, picking a specific design, and possibly modifying it to improve its design, can still present certain challenges that need to be overcome.
For high resolution and high speed imaging, column parallel ADC architecture has become the most widely used ADC in CMOS image sensors. One key challenge to achieving good performance of CMOS image sensors is to reduce noise or other signal offsets from affecting the converted digital data.
With column parallel single slope ADCs, all comparators are connected to a common ramp signal. If there is a large uniform area in an image, many comparators may have the same pixel value. Accordingly, many comparators can toggle at the same time as the input ramp signal reaches the pixel voltage. The toggling comparator outputs can couple to the input ramp signal and create a glitch that can affect the conversion of other pixels in that row.
A method to eliminate this coupling is to cascode transistors to the comparator differential pair. With cascoded transistors, when the comparator outputs toggle the cascode transistor clamps the drain voltage of the input transistor so that there is no switching signal to couple to the input ramp signal. The problem with adding cascodes to the comparator input circuit is that the input signals are not constant and have a wide full scale range. Therefore it is difficult to select an optimal cascode bias voltage.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.